Output Log
To visualize your simulation in Chronos, your simulator must output logs in a specific format via standard output (stdout) or a text file.
Basic Syntax
Chronos parses lines that start with the [ChronosLog] prefix. Lines not matching this prefix are ignored. The fields should be separated by whitespace (tabs or spaces).
1[ChronosLog] <Cycle> <OpName> <Status> <OptionalInfo>| Field | Description | Example |
|---|---|---|
| Prefix | The literal string [ChronosLog]. | [ChronosLog] |
| Cycle | Current simulation cycle (integer). | 1024 |
| OpName | The name of the instruction or function being executed. | loadData |
| Status | The execution state of the instruction (see below). | STALL |
| Info | (Optional) Additional context like addresses, data values, or error messages. | addr=0x8000 |
Status Definitions
Chronos uses three distinct statuses to render the timeline. START is not required; the tool automatically infers the start of an instruction.
EXEC
- Meaning: The instruction is actively executing logic inside the hardware (e.g., multi-cycle arithmetic).
- Usage: Use this when the instruction occupies the pipeline but is not waiting for external resources.
STALL
- Meaning: The instruction is paused, waiting for external resources (e.g., Memory Load/Store, Bus access).
- Usage: Critical for identifying bottlenecks.
DONE
- Meaning: The instruction completed in this cycle.
- Usage: Mandatory. This signals the end of the block. If an instruction finishes in a single cycle, you can output DONE immediately without EXEC or STALL.
The "Continuous Logging" Principle (Important)
Chronos relies on a strict rule: "No Log = No Execution."
- You must output a log every cycle while your custom instruction is active.
- If logs are missing for a range of cycles, Chronos interprets this as a "Gap" (Software Overhead).
- Do not extrapolate. If your instruction takes 10 cycles, print 10 lines of logs.
Example
Implementation Example (C/C++)
The following example uses C syntax to demonstrate the logging logic. Since the actual implementation depends on your specific simulation environment (e.g., SystemVerilog testbench, C++ wrapper for Verilator, or ISS), please adapt this logic to your language of choice.
1// Example logic inside your simulator's step function
2void step_custom_instruction() {
3 // 1. Check if the instruction is finished
4 if (is_finished) {
5 printf("[ChronosLog]\t%d\t%s\tDONE\n", current_cycle, "my_custom_op");
6 return;
7 }
8
9 // 2. Check if the instruction is stalled (e.g., waiting for memory)
10 if (is_memory_stalled) {
11 printf("[ChronosLog]\t%d\t%s\tSTALL\twaiting_mem\n", current_cycle, "my_custom_op");
12 return;
13 }
14
15 // 3. Otherwise, it is executing
16 printf("[ChronosLog]\t%d\t%s\tEXEC\n", current_cycle, "my_custom_op");
17}Sample Output
1[ChronosLog] 100 conv2d EXEC
2[ChronosLog] 101 conv2d STALL addr=0xFF00
3[ChronosLog] 102 conv2d STALL
4[ChronosLog] 103 conv2d DONE result=42Next...
In the next page(Analyze Log), you will learn how to use Chronos with step by step instruction to generate your first time chart.
